wire A, B, C, D, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);
nand a1(NA, A, A);
nand b1(NB, B, B);
nand c1(NC, C, C);
nand d1(ND, D, D);
nand F1(AND1, NA, C);
nand F2(AND2, NA, NB, ND);
nand F3(AND3, C, NB, ND);
nand F4(AND4, A, D, B, NC);
nand h1(F, AND1, AND2, AND3, AND4);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
