2015101401 二位元多工器

module top;

wire A1, A0, SEL, B1, B0, a1out, a2out, n1out ,a3out ,a4out ,out1 ,out0;

system_clock #1600 clock1(A1);
system_clock #800 clock2(A0);
system_clock #400 clock3(SEL);
system_clock #200 clock4(B1);
system_clock #100 clock5(B0);


and a1(a1out, A1, SEL);
and a2(a2out, A0, SEL);
not n1(n1out, SEL);
and a3(a3out, B1, n1out);
and a4(a4out, B0, n1out);
or o1(out1, a1out,a3out);
or o2(out0, a2out,a4out);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1600)$stop;

endmodule