20151021 3位元多工器

module top;

wire A0, A1, A2, B0, B1, B2, NSEL, SEL, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9;
system_clock #200 clock1(A0);
system_clock #100 clock2(B0);
system_clock #800 clock1(A1);
system_clock #400 clock2(B1);
system_clock #3200 clock2(A2);
system_clock #1600 clock2(B2);
system_clock #6400 clock1(SEL);
not b1(NSEL, SEL);
and a1(OUT1, A1, SEL);
and a2(OUT2, B1, NSEL);
or a5(OUT6, OUT1, OUT2);

and a3(OUT3, A0, SEL);
and a7(OUT7, A2, SEL);

and a4(OUT4, B0, NSEL);
and a8(OUT8, B2, NSEL);

or a6(OUT5, OUT3, OUT4);
or a6(OUT9, OUT7, OUT8);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>7000)$stop;

endmodule