20151104 一位元多工器改寫

module top;
  integer ia,ib,is;
  reg  a,b,s;
  wire out;

  mux_behavioral mux1(out,a,b,s);

  initial
    begin
      for (is=0; is<=1; is = is+1)
        begin
          s = is;
          for (ia=0; ia<=1; ia = ia + 1)
            begin
              a = ia;
              for (ib=0; ib<=1; ib = ib + 1)
               begin
                 b = ib;
                 #1 $display("a=%d b=%d s=%d   out=%d",a,b,s,out);
               end
            end
        end
    end
endmodule

module mux_behavioral(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;
 wire  A,B,SEL;
 reg    OUT;

  always @(A or B or SEL)
   OUT = (A & SEL)|(B & ~SEL );
endmodule

2015/10/28 2+2=4位元多工器

module top;

wire [3:0]A,SEL,B,OUT;

system_clock #100 clock1(A[1]);
system_clock #200 clock2(A[0]);
system_clock #6400 clock3(SEL);
system_clock #400 clock4(B[1]);
system_clock #800 clock5(B[0]);
system_clock #1600 clock6(A[2]);
system_clock #3200 clock7(B[2]);
system_clock #800 clock8(A[3]);
system_clock #6400 clock9(B[3]);
mux2 M32(OUT[3:2], A[3:2], B[3:2], SEL);

mux2 M10(OUT[1:0], A[1:0], B[1:0], SEL);

endmodule


module mux2(OUT, A, B, SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi (OUT[1], A[1], B[1], SEL);
mux lo (OUT[0], A[0], B[0], SEL);
endmodule


module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule



module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>12800)$stop;

endmodule

20151021 3位元多工器

module top;

wire A0, A1, A2, B0, B1, B2, NSEL, SEL, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9;
system_clock #200 clock1(A0);
system_clock #100 clock2(B0);
system_clock #800 clock1(A1);
system_clock #400 clock2(B1);
system_clock #3200 clock2(A2);
system_clock #1600 clock2(B2);
system_clock #6400 clock1(SEL);
not b1(NSEL, SEL);
and a1(OUT1, A1, SEL);
and a2(OUT2, B1, NSEL);
or a5(OUT6, OUT1, OUT2);

and a3(OUT3, A0, SEL);
and a7(OUT7, A2, SEL);

and a4(OUT4, B0, NSEL);
and a8(OUT8, B2, NSEL);

or a6(OUT5, OUT3, OUT4);
or a6(OUT9, OUT7, OUT8);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>7000)$stop;

endmodule

2015101402 1X2=2位元多工器

module top;

wire A1, A0, SEL, B1, B0,out1 ,out0

system_clock #1600 clock1(A1);
system_clock #800 clock2(A0);
system_clock #400 clock3(SEL);
system_clock #200 clock4(B1);
system_clock #100 clock5(B0);

mux M1(out1, A1, B1, SEL);
mux M0(out0, A0, B0, SEL);
endmodule



module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule



module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1600)$stop;

endmodule

2015101401 二位元多工器

module top;

wire A1, A0, SEL, B1, B0, a1out, a2out, n1out ,a3out ,a4out ,out1 ,out0;

system_clock #1600 clock1(A1);
system_clock #800 clock2(A0);
system_clock #400 clock3(SEL);
system_clock #200 clock4(B1);
system_clock #100 clock5(B0);


and a1(a1out, A1, SEL);
and a2(a2out, A0, SEL);
not n1(n1out, SEL);
and a3(a3out, B1, n1out);
and a4(a4out, B0, n1out);
or o1(out1, a1out,a3out);
or o2(out0, a2out,a4out);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1600)$stop;

endmodule

多工器2

多工器1