20151125 4位元 結構模式

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

20151125 4位元全加法器

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

ADDER1

module top;
system_clock #400 clock1(C);
system_clock #200 clock2(A);
system_clock #100 clock3(B);

adder1 m1(A, B, C, Cout, Sum);

endmodule

module adder1(A, B, C,Cout,Sum);
output Cout, Sum;
input A, B, C;
not I1(Anot,A);
not I2(Bnot,B);
not I3(Cnot,C);

and I4(S1,A,B);
and I5(S2,B,C);
and I6(S3,A,C);
and I7(S4,A,B,C);
and I8(S5,A,Bnot,Cnot);
and I9(S6,Anot,B,Cnot);
and I10(S7,Anot,Bnot,C);

or I11(Cout,S1,S2,S3);
or I12(Sum,S4,S5,S6,S7);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

一位元加法器行為模式設計與測試

module test_adder1;

 reg a,b;
 reg carry_in ;
 wire sum;
 wire carry_out;

 adder1_behavorial A1(carry_out, sum, a, b, carry_in);

 initial
  begin

    carry_in = 0; a = 0; b = 0;
    # 100 if ( carry_out !== 0 | sum !== 0)
                $display(" 0+0+0=00 sum is WRONG!");
              else
                $display(" 0+0+0=00 sum is RIGHT!");
    carry_in = 0; a = 0; b = 1;
    # 100 if ( carry_out  !== 0 | sum !== 1)
               $display(" 0+0+1=01 sum is WRONG!");
              else
               $display(" 0+0+1=01 sum is RIGHT!");
    carry_in = 0; a = 1; b = 0;
    # 100 if ( carry_out  !== 0 | sum !== 1)
               $display(" 0+1+0=01 sum is WRONG!");
              else
               $display(" 0+1+0=01 sum is RIGHT!");
   carry_in = 0; a = 1; b = 1;
    # 100 if ( carry_out  !== 1 | sum !== 0)
               $display(" 0+1+1=10 sum is WRONG!");
              else
               $display(" 0+1+1=10 sum is RIGHT!");
    carry_in = 1; a = 0; b = 0;
    # 100 if ( carry_out  !== 0 | sum !== 1)
               $display(" 1+0+0=01 sum is WRONG!");
              else
              $display(" 1+0+0=01 sum is RIGHT!");
    carry_in = 1; a = 0; b = 1;
    # 100 if ( carry_out  !== 1 | sum !== 0)
               $display(" 1+0+1=10 sum is WRONG!");
              else
               $display(" 1+0+1=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 0;
    # 100 if ( carry_out  !== 1 | sum !== 0)
               $display(" 1+1+0=10 sum is WRONG!");
              else
               $display(" 1+1+0=10 sum is RIGHT!");
    carry_in = 1; a = 1; b = 1;
    # 100 if ( carry_out  !== 1 | sum !== 1)
               $display(" 1+1+1=11 sum is WRONG!");
              else
               $display(" 1+1+1=11 sum is RIGHT!");



             

    $finish;


  end
endmodule



module adder1_behavorial (carry_out, sum, a, b, carry_in);
 input a, b, carry_in;
 output carry_out, sum;
  assign sum = (a^b)^carry_in;
  assign carry_out =  (a^b)&carry_in|(a&b);
endmodule

20151104 二位元多工器 改寫

module top;
  integer ia,ib,is,ie,ig;
  reg  a,b,s,e,g;
  wire out,out1;

  mux_behavioral mux1(out,a,b,s);
  mux_behavioral mux2(out1,s,e,g);
  initial
    begin
      for (is=0; is<=1; is = is+1)
        begin
          s = is;
          for (ib=0; ib<=1; ib = ib + 1)
            begin
              b = ib;
              for (ia=0; ia<=1; ia = ia + 1)
               begin
                 a = ia;
                   for (ie=0; ie<=1; ie = ie + 1)
                     begin
                     e = ie;
                       for (ig=0; ig<=1; ig = ig + 1)
                           begin
                              g = ig;
                       #10 $display("s=%d b=%d a=%d   out=%d e=%d g=%d   out1=%d",s,b,a,e,g,out,out1);
               end
            end
        end
    end
    end
    end
endmodule
module mux_behavioral(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;
 wire  A,B,SEL;
 reg    OUT;


  always @(A or B or SEL)
   OUT = (A & SEL)|(B & ~SEL );
endmodule

20151104 一位元多工器改寫

module top;
  integer ia,ib,is;
  reg  a,b,s;
  wire out;

  mux_behavioral mux1(out,a,b,s);

  initial
    begin
      for (is=0; is<=1; is = is+1)
        begin
          s = is;
          for (ia=0; ia<=1; ia = ia + 1)
            begin
              a = ia;
              for (ib=0; ib<=1; ib = ib + 1)
               begin
                 b = ib;
                 #1 $display("a=%d b=%d s=%d   out=%d",a,b,s,out);
               end
            end
        end
    end
endmodule

module mux_behavioral(OUT, A, B, SEL);
 output OUT;
 input A,B,SEL;
 wire  A,B,SEL;
 reg    OUT;

  always @(A or B or SEL)
   OUT = (A & SEL)|(B & ~SEL );
endmodule