integer ia,ib,is,ie,ig;
reg a,b,s,e,g;
wire out,out1;
mux_behavioral mux1(out,a,b,s);
mux_behavioral mux2(out1,s,e,g);
initial
begin
for (is=0; is<=1; is = is+1)
begin
s = is;
for (ib=0; ib<=1; ib = ib + 1)
begin
b = ib;
for (ia=0; ia<=1; ia = ia + 1)
begin
a = ia;
for (ie=0; ie<=1; ie = ie + 1)
begin
e = ie;
for (ig=0; ig<=1; ig = ig + 1)
begin
g = ig;
#10 $display("s=%d b=%d a=%d out=%d e=%d g=%d out1=%d",s,b,a,e,g,out,out1);
end
end
end
end
end
end
endmodule
module mux_behavioral(OUT, A, B, SEL);
output OUT;
input A,B,SEL;
wire A,B,SEL;
reg OUT;
always @(A or B or SEL)
OUT = (A & SEL)|(B & ~SEL );
endmodule
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